PRELIMINARY
CYW54907
17.3 SDIO Interface Timing
17.3.1 SDIO Default-Speed Mode Timing
SDIO default-speed (DS) mode timing is shown by the combination of Figure 23 and Table 46.
Figure 23. SDIO Bus Timing (Default-Speed Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Table 46. SDIO Bus Timinga Parameters (Default-Speed Mode)
Parameter Symbol
Minimum
Typical
Maximum
Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
fPP
fOD
tWL
0
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
10
10
–
Clock high time
tWH
tTLH
tTHL
–
ns
Clock rise time
10
10
ns
Clock low time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Document Number: 002-19312 Rev. *C
Page 77 of 95
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