PRELIMINARY
CYW54907
2
17.2 I S Master and Slave Mode TX Timing
Figure 20 and Table 44 provide the I2S Master mode transmitter timing.
Figure 20. I2S Master Mode Transmitter Timing
T
t
HC = 0.35T
t
RC
V
V
t
H = 2.0V
L = 0.8V
LC = 0.35T
I2S_SCLK
t
htr = 0
t
dtr = 0.8T
I2S_SDATO
and I2S_LRCK
T = Clock period.
Ttr = Minimum allowed clock period for transmitter.
T > Ttr.
tRC is only relevant for transmitters in Slave mode.
Figure 21 and Table 44 provide the I2S Slave mode receiver timing.
Figure 21. I2S Slave Mode Receiver Timing
T
tHC = 0.35T
V
V
H = 2.0V
L = 0.8V
tLC = 0.35T
tsr = 0.2T
I2S_SCLK
thr = 0
I2S_SDATAI
and I2S_LRCK
T = Clock period.
Tr = Minimum allowed clock period for the transmitter.
T > Tr.
Document Number: 002-19312 Rev. *C
Page 75 of 95
CYPRESS [ CYPRESS ]
