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BCM54907 参数 Datasheet PDF下载

BCM54907图片预览
型号: BCM54907
PDF下载: 下载PDF文件 查看货源
内容描述: [WICED™ IEEE 802.11 a/b/g/n/ac SoC with an Embedded Applications Processor]
分类和应用:
文件页数/大小: 95 页 / 1802 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
CYW54907  
17.1.3 RMII Receive Packet Timing  
Figure 18 and Table 42 provide the RMII receive packet timing.  
Figure 18. RMII Receive Packet Timing  
REF_CLK  
CRS_DV  
RXD[1]  
RXD[0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
0
0
/J/  
/K/  
Preamble  
SFD  
Data  
Table 42. RMII Receive Packet Timing  
Parameter  
Symbol  
Minimum  
Typical  
Maximum  
Unit  
ns  
REF_CLK Cycle Time  
2
20  
RXD[1:0], RXER, CRS_DV Output delay from REF_CLK rising  
10  
ns  
Notes:  
1. In 10 Mbps mode, there are ten REF_CLK periods per data period.  
2. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity  
buffering.  
Document Number: 002-19312 Rev. *C  
Page 73 of 95  
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