PRELIMINARY
CYW54907
17. Interface Timing and AC Characteristics
17.1 Ethernet MAC (MII/RMII) Interface Timing
17.1.1 MII Receive Packet Timing
Figure 16 and Table 40 provide the MII receive packet timing.
Figure 16. MII Receive Packet Timing
t404
t402
t401
t403
RXC
R XDV
RXD[3:0]
Table 40. MII Receive Packet Timing Parameters
Parameter Description
t401
Minimum
Typical
Maximum
Units
ns
RXDV and RXD[3:0] to RXC rising setup time
RXC clock period (10BASE-T mode)
RXC clock period (100BASE-TX mode)
RXC low/high time (10BASE-T mode)
RXC low/high time (100BASE-TX mode)
RXDV and RXD[3:0] to RXC rising hold time
Duty cycle
10
–
–
400
40
–
–
–
t402
ns
–
–
ns
t403
160
16
10
40
240
24
–
ns
–
ns
t404
–
–
ns
50
60
%
17.1.2 MII Transmit Packet Timing
Figure 17 and Table 41 provide the MII transmit packet timing.
Figure 17. MII Transmit Packet Timing
T X C
T X E N
T X D [3:0 ]
Table 41. MII Transmit Packet Timing Parameters
Parameter
t405
t406
Description
Minimum
Typical
Maximum
Units
TXC high to TXEN and TXD[3:0] valid
TXC high to TXEN and TXD[3:0] invalid (hold)
0
0
–
–
25
–
ns
ns
Document Number: 002-19312 Rev. *C
Page 72 of 95
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