AIS Baseband Processor
CMX910
5.9
Interrupt Generator
The CMX910 has sixteen internal interrupt sources which provide status information to the µC – these are
accessible through a C-BUS read register. The interrupt flags may also be enabled to drive the open-drain
IRQN output pin.
Interrupt register: 16-bit read only.
C-BUS Address $80
Register gets set to $0080 on reset.
15
14
13
12
11
Tx
10
9
8
7
6
5
4
3
2
1
0
Bit:
Spcl
Aux
Rx2
Rx1
FSK
Rx2
Rx1
Tx
FSK
Rx2
Rx1
Rx2
Burst Burst
Avail. Avail.
Rx1
Tx
Done
Nudge
Done
Cmnd ADC State State FIFO FIFO FIFO FIFO FIFO FIFO FIFO FIFO
Done Done Alert Alert Error Error Error Error Trigger Trigger Trigger Trigger
Interrupt register b15: Special Command Done
This bit goes high to indicate that a command issued to the Special Command Interface has
completed. This bit gets cleared automatically after being read.
Interrupt register b14: Aux ADC Done
This bit goes high to indicate that the Auxiliary ADC has finished doing a sequence of conversions
after an ADC_Convert command was issued. This bit gets cleared automatically after being read.
Interrupt register b13: Rx2 State Alert
This bit goes high in AIS burst mode only, and indicates that the Rx2 channel has finished
receiving a message – the Rx2_Status register can be read to determine whether a valid
message was received or an error occurred. This bit gets cleared automatically after being read.
Interrupt register b12: Rx1 State Alert
This bit goes high in AIS burst mode only, and indicates that the Rx1 channel has finished
receiving a message – the Rx1_Status register can be read to determine whether a valid
message was received or an error occurred. This bit gets cleared automatically after being read.
Interrupt register b11: Tx FIFO Error
This bit goes high to indicate that an overflow or an underflow error has occurred in the Tx
channel FIFO. This can be determined by reading the Tx_Status register (bits 15 and 14). This bit
gets cleared automatically after being read.
Interrupt register b10: FSK FIFO Error
This bit goes high to indicate that an overflow or an underflow error has occurred in the FSK
channel FIFO. This can be determined by reading the FSK_Status register (bits 15 and 14). This
bit gets cleared automatically after being read.
Interrupt register b9: Rx2 FIFO Error
This bit goes high to indicate that an overflow or an underflow error has occurred in the Rx2
channel FIFO. This can be determined by reading the Rx2_Status register (bits 15 and 14). This
bit gets cleared automatically after being read.
Interrupt register b8: Rx1 FIFO Error
This bit goes high to indicate that an overflow or an underflow error has occurred in the Rx1
channel FIFO. This can be determined by reading the Rx1_Status register (bits 15 and 14). This
bit gets cleared automatically after being read.
© 2009 CML Microsystems Plc
46
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
