AIS Baseband Processor
CMX910
5.10
Device Enable Port
The device enable port (pins ENAB5 – ENAB0) provides for the timed control of peripheral RF circuits that
is required for TDMA operation. The ENAB5 – ENAB0 pins are digital outputs and will typically be used as
enabling signals for the external receiver/transmitter circuits and power amplifier. By default, the CMX910
will automatically control all six device enable pins. In conjunction with the automatic PA ramping feature
of DAC0, this greatly simplifies the control of the RF circuits. If desired, individual pins of the device
enable port may be configured to be under µC control via the C-BUS.
ENAB register: 8-bit write only.
C-BUS Address $90
All bits cleared to 0 on reset.
7
6
5
4
3
2
1
0
Bit:
Reserved, ENAB ENAB ENAB ENAB ENAB ENAB
set to 00
5
4
3
2
1
0
ENAB register b5-0: ENAB5 – ENAB0 Data
By writing to the bits in the ENAB register, the µC can directly control the logic state of the
corresponding ENAB5 – ENAB0 pins. This only happens for those pins which have been
configured to be under C-BUS control, i.e. those whose corresponding bit in the ENAB_Mask
register is set high. Note: if the corresponding bit in the ENAB_Invert register is also set high, the
logic level appearing at the device pin will be the inverse of the data in the ENAB register bit.
ENAB_Mask register: 8-bit write only.
C-BUS Address $91
All bits cleared to 0 on reset.
7
6
5
4
3
2
1
0
Bit:
ENAB ENAB ENAB ENAB ENAB ENAB
Mask Mask Mask Mask Mask Mask
Reserved,
set to 00
5
4
3
2
1
0
ENAB_Mask register b5-0: ENAB5 – ENAB0 Mask
Each bit that is set high in the ENAB_Mask register causes the corresponding device enable pin
to be under direct control of the µC. Those bits in the ENAB_Mask register that are low cause the
corresponding pin to be under the automatic control of the CMX910.
ENAB_Invert register: 8-bit write only.
C-BUS Address $92
All bits cleared to 0 on reset.
7
6
5
4
3
2
1
0
Bit:
ENAB ENAB ENAB ENAB ENAB ENAB
Invert Invert Invert Invert Invert Invert
Reserved,
set to 00
5
4
3
2
1
0
ENAB_Invert register b5-0: ENAB5 – ENAB0 Inversion Control
The polarity of the ENAB5 – ENAB0 pins are individually controlled through this register. By
setting a bit high in the ENAB_Invert register, the logic level appearing on the corresponding
device enable pin will be inverted. This inversion is applied whether the pin is under µC control or
automatic CMX910 control.
© 2009 CML Microsystems Plc
48
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
