AIS Baseband Processor
CMX910
situation arises because the AIS specification allows a transmitter’s NRZI encoder to start in either of its
two quiescent states, and the pre-NRZI encoded training bytes can also be one of two different types ($55
or $AA). Therefore, for any particular message, the three received training bytes in AIS raw mode will all
be either $33, $66, $99 or $CC, although the first few bits may be corrupted depending on the power-up
characteristics of the remote transmitter and local receiver circuits.
In AIS raw mode, whenever an Rx1 state reset is performed (by setting Rx1_Control b0 = 1) the channel
state (Rx1_Status b2-0) becomes Idle. This changes to Receiving when the first valid training sequence
and start flag have been detected, where it remains until another Rx1 state reset occurs.
5.6.3 AIS Burst Mode Receive
The operation of receive channel Rx1 in AIS burst mode is described below (the operation of receive
channel Rx2 in AIS burst mode is essentially identical to that of Rx1).
In AIS burst mode the Rx1 channel state (Rx1_Status b2-0) changes to Receiving when a valid training
sequence and start flag are detected. The CMX910 then performs NRZI decoding and bit destuffing on
the received data stream, and calculates the CRC checksum. At the end of the message the receive
channel state changes from Receiving to either Idle or one of four error states (below). At the same time,
an “Rx1 State Alert” interrupt is flagged.
The four error conditions that the CMX910 can detect in a received message (in burst mode) are:
1. Message too long or missing end flag. This indicates that the received message, after bit
destuffing, is too long to fit into an internal 172 byte message buffer. This condition could be
caused by a missing or corrupted end flag.
2. CRC mismatch. This indicates that the received frame checksum does not match that
calculated by the CMX910, most probably as the result of one or more message bits being
corrupted.
3. New frame header found but both message buffers full. This happens if both internal
message buffers are in use when another message arrives. This is caused by a failure of the
µC to read the received messages out quickly enough.
4. End flag not on byte boundary. This indicates that the received message, after bit destuffing,
is not a multiple of 8 bits. Assuming that the message was transmitted correctly, the most
probable cause of this error is an end flag being missed due to noise, and a subsequent
message’s start flag being misidentified as the expected end flag.
If one of these four error conditions is detected in a received message the CMX910 discards the message
data and, after flagging the “Rx1 State Alert” interrupt, continues searching for the next training sequence
and start flag.
If a message with no error is found the Rx1 channel state changes from Receiving to Idle (causing an
“Rx1 State Alert” interrupt); the decoded message, comprising the three training sequence bytes, start
flag, message payload, end flag and CRC bytes, is then copied to one of the CMX910’s internal message
buffers. When its turn comes around to be read out, an “Rx1 Burst Available” interrupt is generated. At
this point the CMX910 updates the registers Rx1_Slot, Rx1_Sample, Rx1_Bytes, Rx1_FreqErr and
Rx1_RSSI with the values calculated for that message, then begins transferring the data from the internal
message buffer to Rx1_FIFO. Note: a new message will only generate an “Rx1 Burst Available” interrupt
when any previous message has been read out from Rx1_FIFO in its entirety.
For any particular message, the three received (NRZI-decoded) training bytes in AIS burst mode will all
be either $55 or $AA depending on the configuration of the remote transmitter, although the first few bits
may be corrupted depending on the power-up characteristics of the remote transmitter and local receiver
s.
circuit
© 2009 CML Microsystems Plc
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