AIS Baseband Processor
CMX910
Tx_Status register: 16-bit read only.
C-BUS Address $22
Register gets set to $0080 on reset.
15
Tx
14
Tx
13
12
11
10
9
8
7
6
0
5
0
4
0
3
2
1
0
Bit:
Tx
FIFO
Trigger
Over- Under-
flow flow
Tx FIFO Fill Level
Tx State
Tx_Status register b15: Tx Overflow
This bit gets set high if the µC attempts to write to the Tx FIFO when it is already full, indicating
that data has been lost. A Tx Overflow does not automatically cause the transmission to be
aborted, this must be done separately by the the µC if necessary. The Tx Overflow bit gets
cleared as soon as the Tx_Status register has been read.
Tx_Status register b14: Tx Underflow
This bit gets set high if the µC does not send data to the CMX910 quickly enough during
transmission, causing a data famine in the Tx channel (this does not happen in AIS burst mode
since an entire message must be conveyed to the CMX910 before transmission starts). A Tx
Underflow does not automatically cause the transmission to be aborted, this must be done by the
the µC. Failure to do this will result in erroneous data being transmitted. The Tx Underflow bit gets
cleared as soon as it has been read.
Note: Tx_Status b15 and b14 are ORed together for the purpose of generating an interrupt.
Tx_Status register b13-8: Tx FIFO Fill Level
This shows how many bytes are in the Tx FIFO. The number will be in the range 0 to 32.
Tx_Status register b7: Tx FIFO Trigger
This bit will be high if the Tx FIFO fill level is less than or equal to the Tx threshold level, i.e.
Tx_Status[13-8] ≤ Tx_FIFO_Threshold[4-0]. This bit can generate an interrupt.
Tx_Status register b3-0: Tx State
Indicates the current transmitter state. If a transmission has not been requested the Tx state will
be Idle, otherwise the Tx State bits change to reflect the progress of the transmission. After a
transmission has completed the Tx State bits will either indicate that the transmission was
successful, or will indicate the nature of any problem encountered.
b3
b2
b1
b0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Idle
Building message buffer (burst mode)
Message buffer ready (burst mode)
Tx pending
Tx in progress
Tx aborted – carrier sensed (CSTDMA)
Tx aborted – buffer not ready (burst mode)
Tx aborted – message too long (burst mode)
Chained message in progress
© 2009 CML Microsystems Plc
20
D/910/6
CMLMICRO [ CML MICROCIRCUITS ]
