TDMA Digital Radio Processor
CMX7161
depending on the setting in the Modem Options - $69, write register. The CMX7161 continues to receive
data until another mode is selected, or Rx Data mode is re-written to the Modem Control register to restart
frame sync search.
7.8.8 Slotted Data Mode (1111)
In slotted mode operation, a two-slot TDMA structure is supported with slots. Each 30ms slot can be
designated a receive, transmit or idle slot using the upper byte of the Modem Control register. Data from
Receive slots is returned via the register, and data for Transmit slots should be loaded via the Transmit
FIFO - $48, streaming write register. All 264 bits in each burst are transferred including the frame sync /
signalling bits. Received data can be returned to the host either as hard-decision bits or as 4-bit soft-
decision log likelihood ratio (LLR) metrics.
Slot timing can be established from the received signal (using received frame syncs as the reference) or
from a local reference (i.e. the host). Once the slot timing has been established the CMX7161 will maintain
its own internal slot clock using corrections from received bursts where available. The host can adjust
transmit timing in either slot using the Slot Control - $68, write register.
A host IRQ is issued for each slot as a timing reference and to indicate when data should be loaded for
Transmit slots. If a local slot timing reference is in use the CMX7161 a GPIO pin can be configured as slot
timing input or the CMX7161 can begin transmission immediately on command. A GPIO can also
optionally be designated as a slot timing output reference.
7.9
Signal Level Optimisation
The internal signal processing of the CMX7161 will operate with wide dynamic range and low distortion
only if the signal level at all stages in the signal processing chain is kept within the recommended limits.
For a device working from a 3.3V supply the signal range which can be accommodated without distortion
is specified in 8.1.3 Operating Characteristics. Signal gain and DC offset can be manipulated as follows:
7.9.1 Transmit Path Levels
The Coarse Output Gain setting has a range of +6dB to –14.2dB in 0.2dB steps. The Fine Output Gain
setting can be used to achieve precise control.
The Mod 1 and Mod 2 outputs may be independently inverted by setting negative Fine Output Gain values.
DC offsets may also be applied to each output, but care must be taken that the combination of gain
settings and DC offset do not cause the signal to clip at any point in the processing sequence. The order
of processing is Fine Gain, followed by DC offset, followed by Coarse Gain.
See also:
Mod 2/1 Output Control - $5D, $5E, write
Mod 1/2 Output Power Control - $B3, write
Mod 1/2 Output Coarse Gain - $B4, $B5 write
7.9.2 Receive Path Levels
The Coarse Input Gain setting has a range of 0dB to +22.4.dB in 3.2dB steps
When receiving I/Q format signals, inverting one of the I/Q pair has a similar effect to swapping I with Q.
DC offsets can be removed by the CMX7161: the offset to remove can be specified by the host or
calculated automatically by the CMX7161. It should be noted that if the maximum allowable signal input
level is exceeded, signal distortion will occur regardless of the internal DC offset removal.
See also:
I/Q Input Control - $5F, $60 write
I/Q Input Power Control - $B0, write
I/Q Input Coarse Gain - $B1, $B2 write
2013 CML Microsystems Plc
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CMLMICRO [ CML MICROCIRCUITS ]
