TDMA Digital Radio Processor
CMX7161
264 bits
48 bits
108 bits
108 bits
Payload
Sync or
Embedded
Signaling
Payload
5.0 msec
27.5 msec
30.0 msec
Figure 14 Slot Structure
When searching for frame synchronisation CMX7161 is able to scan for any combination of the ten
synchronisation words defined by TS 102 361 by setting the appropriate bits in the Modem Options - $69,
write register. In order to acquire system slot timing from a received signal an initial frame sync is required.
However once slot timing has been established the CMX7161 will maintain its own internal slot and symbol
timing reference, allowing it to receive data bursts in slots that do not contain a synchronisation word.
$755FD7DF75F7
FS0: BS voice
$DFF57D75DF5D FS1: BS data
$7F7D5DD57DFD FS2: MS voice
$D5D7F77FD757
$77D55F7DFD77
$5D577F7757FF
FS3: MS data
FS4: MS reverse channel
FS5: TDMA direct slot 1 voice
$F7FDD5DDFD55 FS6: TDMA direct slot 1 data
$7DFFD5F55D5F FS7: TDMA direct slot 2 voice
$D7557F5FF7F5
FS8: TDMA direct slot 2 data
$DD7FF5D757DD FS9: (reserved)
The CMX7161 transmit burst timing is linked directly to timing of the received synchronisation word. The
timing may be adjusted by timing parameters that can be accessed via the programming registers (P2.x),
Timing relationships between the various signals are shown in Figure 15, referring to the figure the
following parameters apply as follows:
A = value set in P2.0
B = value set in P2.1
C = value set in P2.2
D = valve set in P2.3
E = constant offset between received synchronisation word and internal timing reference.
The value programmed in each register has a resolution of 1/480 µs, e.g. $C0 = 192 (decimal) = 0.4 ms.
2013 CML Microsystems Plc
Page 24
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
