TDMA Digital Radio Processor
CMX7161
SYSPLLCON0
SYSPLLCON1
SYSPLLCON2
Ref Clk
÷1 to
512
VCO
Ph
Q
÷1 or
÷2
Det
Pump
÷1 to
4096
Local Clk
VCO Clk
Loop
Filt
Lock
Timer
SYSCLK PLL
PLL ClkIn
PLL ClkOut
SYSCLK IN
1
SYSCLKDIV1 b15, 13, 5-0
0
2
SYSCLK1
DIVIDER
÷1 to 64
SYSCLKCON b1-0
1
SYSCLK1
0
SYSCLKDIV1 b11-6
SYSCLKCON b3-2
PHASE
SHIFT
SYSCLKDIV2 b15, 13, 5-0
2
1
0
SYSCLK2
DIVIDER
÷1 to 64
SYSCLK2
1
0
SYSCLKDIV1 b12
SYSCLKCON b5-4
Figure 17 Digital System Clock Generation Schemes
See:
Program Block 1 – Clock Control
2013 CML Microsystems Plc
Page 30
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
