TDMA Digital Radio Processor
CMX7161
7.8.1 Sleep Mode (0000)
Sleep mode is the device’s lowest power state. While in Sleep mode the Programming - $6A, write register
is available to configure device parameters.
7.8.2 Tx Set-up Mode (1001)
A repeating data sequence is modulated and sent continuously. The data sequence can be selected using
bits 5-4 of the Modem Control Register ($6B) from:
$5F repeating (for Tx calibration as specified by TS 102 361)
$55 $55 $55 $55 $FF $FF $FF $FF (sixteen +3 symbols, sixteen -3 symbols)
$55 repeating (continuous +3 symbols)
$7F $7D $5D $D5 $7D $FD (MS Voice frame sync pattern)
7.8.3 Tx PRBS Mode (1010)
A repeating 511-bit PRBS (pseudo random bit sequence) conforming to ITU-T O.153 (Paragraph 2.1) is
modulated and sent continuously.
7.8.4 Tx Data Mode (1011)
Data loaded by the host into the Transmit FIFO is modulated and sent continuously. Data can be
preloaded into the FIFO before setting the device into Tx Data Mode, if required. The host should ensure
that the FIFO does not run empty during transmission.
7.8.5 Rx Set-up Mode (0001)
The received I/Q signals are output on the MOD 1 and 2 outputs with DC offsets and gains applied.
7.8.6 Rx Eye Mode (0010)
The received I/Q signals are channel filtered, demodulated and root-raised-cosine filtered. The resulting
baseband signal is output on MOD 1 along with a symbol-rate clock pulse on MOD 2. These outputs can
be used to generate an eye diagram on a suitable oscilloscope. Note that the clock pulse is generated
locally and is not derived from the input signal.
Figure 16 Received Eye Diagram
7.8.7 Rx Data Mode (0011)
The received I/Q signals are channel filtered, demodulated and root-raised-cosine filtered. The CMX7161
initially scans for frame synchronisation according to the frame syncs selected in the Modem Options -
$69, write register. When a valid frame sync is detected, a Sync interrupt is issued, the detected sync word
is reported in the Receive Status - $7A, read register and the CMX7161 begins demodulating data which is
returned to the host via the Receive FIFO - $4C, streaming read register, including the frame sync and the
108 preceding bits. Data is returned either as hard-decision bits or as 4-bit soft-decision LLR metrics
2013 CML Microsystems Plc
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