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    CL-PS7500FE 参数 Datasheet PDF下载

    CL-PS7500FE图片预览
    型号： CL-PS7500FE
    PDF下载： 下载PDF文件 查看货源
    内容描述： 系统级芯片一个用于互联网设备 [System-on-a Chip for Internet Appliance]
    分类和应用：
    文件页数/大小： 251 页 / 2292 K
    品牌： CIRRUS [ CIRRUS LOGIC ]
     浏览型号CL-PS7500FE的Datasheet PDF文件第5页浏览型号CL-PS7500FE的Datasheet PDF文件第6页浏览型号CL-PS7500FE的Datasheet PDF文件第7页浏览型号CL-PS7500FE的Datasheet PDF文件第8页浏览型号CL-PS7500FE的Datasheet PDF文件第10页浏览型号CL-PS7500FE的Datasheet PDF文件第11页浏览型号CL-PS7500FE的Datasheet PDF文件第12页浏览型号CL-PS7500FE的Datasheet PDF文件第13页  
    CL-PS7500FE
    System-on-a-Chip for Internet Appliance
    13. SOUND FEATURES ........................................................................................................... 133
    13.1
    13.2
    13.3
    Sound ............................................................................................................................................. 133
    The Sound FIFO.............................................................................................................................133
    The Digital Serial Sound Interface..................................................................................................133
    13.3.1
    Timing Formats............................................................................................................... 133
    Features ......................................................................................................................................... 135
    14.1.1
    Flexible Video System ....................................................................................................135
    14.1.2
    Hardware Cursor ............................................................................................................ 135
    14.1.3
    Palette............................................................................................................................. 135
    14.1.4
    Pixel Clock ......................................................................................................................136
    14.1.5
    Display Modes ................................................................................................................ 136
    14.1.6
    Power Management........................................................................................................ 136
    14.1.7
    On-chip Sound System................................................................................................... 136
    Bus Interface .................................................................................................................................. 138
    Setting the FIFO Preload Value ......................................................................................................138
    15.2.1
    Example..........................................................................................................................139
    The Video and Sound Macrocell Registers ....................................................................................140
    Video Palette: Address 0x0 ............................................................................................................142
    Video Palette Address Pointer: Address 0x1 .................................................................................. 142
    LCD Offset Registers: Addresses 0x30 and 0x31 .......................................................................... 143
    Border Color Register: Address 0x4............................................................................................... 144
    Cursor Palette: Addresses 0x5–0x7 ...............................................................................................144
    Horizontal Cycle Register (HCR): Address 0x80 ............................................................................145
    Horizontal Sync Width Register (HSWR): Address 0x81................................................................ 145
    Horizontal Border Start Register (HBSR): Address 0x82 ............................................................... 145
    Horizontal Display Start Register (HDSR): Address 0x83 ..............................................................146
    Horizontal Display End Register (HDER): Address 0x84 ...............................................................146
    Horizontal Border End Register (HBER): Address 0x85 ................................................................ 146
    Horizontal Cursor Start Register (HCSR): Address 0x86 ............................................................... 147
    Horizontal Interlace Register (HIR): Address 0x87.........................................................................147
    Horizontal Test Registers: Addresses 0x88 and 0x8H.................................................................... 147
    Vertical Cycle Register (VCR): Address 0x90 ................................................................................ 147
    Vertical Sync Width Register (VSWR): Address 0x91 .................................................................... 148
    Vertical Border Start Register (VBSR): Address 0x92....................................................................148
    Vertical Display Start Register (VDSR): Address 0x93................................................................... 148
    Vertical Display End Register (VDER): Address 0x94 .................................................................... 149
    Vertical Border End Register (VBER): Address 0x95 ..................................................................... 149
    Vertical Cursor Start Register (VCSR): Address 0x96.................................................................... 149
    Vertical Cursor End Register (VCER): Address 0x97..................................................................... 150
    Vertical Test Registers: Addresses 0x98, 0x9A and 0x9C..............................................................150
    External Register (EREG): Address 0xC........................................................................................ 151
    Frequency Synthesizer Register (FSYNREG): Address 0xD ......................................................... 152
    Control Register (CONREG): Address 0xE ....................................................................................153
    Data Control Register (DCTL): Address 0xF .................................................................................. 154
    Sound Frequency Register (SFR): Address 0xB0 .......................................................................... 154
    Sound Control Register (SCTL): Address 0xB1 .............................................................................155
    14. VIDEO AND SOUND MACROCELL .................................................................................. 135
    14.1
    15. VIDEO MACROCELL INTERFACE.................................................................................... 138
    15.1
    15.2
    16. THE VIDEO SOUND AND PROGRAMMER’S MODEL .................................................... 140
    16.1
    16.2
    16.3
    16.4
    16.5
    16.6
    16.7
    16.8
    16.9
    16.10
    16.11
    16.12
    16.13
    16.14
    16.15
    16.16
    16.17
    16.18
    16.19
    16.20
    16.21
    16.22
    16.23
    16.24
    16.25
    16.26
    16.27
    16.28
    16.29
    16.30
    8
    TABLE OF CONTENTS
    ADVANCE DATA BOOK v2.0
    June 1997

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