CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.26 Frequency Synthesizer Register (FSYNREG): Address 0xD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 0 1
X X X X X X X X
X X X X X X X X
modulus r
(ref clock)
r test bits
modulus v
(VCO clock)
v test bits
The CL-PS7500FE can drive a VCO to provide a suitable input frequency for the pixel clock derived from
a reference clock. This is achieved by dividing the reference clock by modulus r, and the VCO clock by
modulus v, then comparing the resultant frequencies. Refer to Chapter 12 for a more detailed explanation.
The two moduli, r and v, are each 6-bit values, and are programmed in this register. Each counter has 2
associated test bits that are normally programmed to ‘0’.
Setting bit 6
Setting bit 7
Setting bit 14
Setting bit 15
forces the phase comparator high, which drives PCOMP high.
clears the r-modulus counter.
forces the phase comparator low, which drives PCOMP low.
clears the v-modulus counter.
To reduce power consumption, program this register with large values when the frequency synthesizer is
not in use. In particular, do not set bits 6 and 14 at the same time.To get a modulus of r, program the value
(r − 1) into FSYNREG. Do the same for the v modulus.
152
June 1997
THE VIDEO SOUND AND PROGRAMMER’S MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
