CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.10 Horizontal Display Start Register (HDSR): Address 0x83
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 0 0 0
0 0 1 1
X X X X X X X X X X X X 0
HDSR value
This register defines the time, in pixels, from the start of the HSYNC pulse to the start of the video display.
This is a 14-bit register of which the bottom bit must be programmed to ‘0’. If N pixels are required in this
time, then program the value (N − 18) into the HBSR (N must be a multiple of 2).
16.11 Horizontal Display End Register (HDER): Address 0x84
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 0 0 0
0 1 0 0
X X X X X X X X X X X X 0
HDER value
This register defines the time, in pixels, from the start of the HSYNC pulse to the end of the video display
(that is, the first pixel that is not display). This is a 14-bit register of which the bottom bit must be pro-
grammed to 0. If N pixels are required in this time, then program the value (N − 18) into the HBER (N must
be a multiple of 2).
16.12 Horizontal Border End Register (HBER): Address 0x85
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 0 0 0
0 1 0 1
X X X X X X X X X X X X 0
HBER value
This register defines the time, in pixels, from the start of the HSYNC pulse to the end of the border display
(that is, the first pixel that is not border). This is a 14-bit register of which the bottom bit must be pro-
grammed to ‘0’. If N pixels are required in this time, then program the value (N − 12) into the HBER (N
must be a multiple of 2.) Again, if no border is required, this register must still be programmed so that N
= N
.
HBER
HDER
146
June 1997
THE VIDEO SOUND AND PROGRAMMER’S MODEL
ADVANCE DATA BOOK v2.0
CIRRUS [ CIRRUS LOGIC ]
