CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.4 LCD Offset Registers: Addresses 0x30 and 0x31
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 1 1 0 0 0 0
0
0 0 0 X X X
X
test bit (must be zero)
msel[2:0] (test bits – must be zero)
Off_5
Off_2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0 0 1 1 0 0 0 1
X X X X X X X X
Off_15
Off_9
These two 8-bit registers define the offsets required for driving a dual panel LCD screen. Register 0
defines the offsets for the five and two frame duty cycle gray scales, as well as reset and test mode bits.
Register 1 defines the offsets for the nine- and fifteen-frame, duty-cycle grayscales.
The registers values are dependent upon the size of the LCD screen to be driven, and are calculated as
shown in Equation 16-1.
Off_15 = (3xL + 8) mod 15
Off_9 = (7xL + 4) mod 9
Off_5 = (1xL + 3) mod 5
Off_2 = 0
Equation 16-1
where,
L is the number of lines in the upper panel of the dual-panel LCD screen.
Bits 7:4 of register 0 are only used in test mode, and must all be set to ‘0’ in normal operation.
msel[2:0] are test bits and must be programmed low.
June 1997
143
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
CIRRUS [ CIRRUS LOGIC ]
