CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.25 External Register (EREG): Address 0xC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 0 0
X X X X
X X
X
X X X X X X X
X X X
EREG[1:0]
0 ECLK off
1 ECLK on
EREG[7:4]
pedon[2:0]
Red pedestal on
Green pedestal on
Blue pedestal on
0 dac DACs power-down
1 dac DACs on
0 lcd grayscale off
1 lcd grayscale on
0 hrm HiRes mode off
1 hrm HiRes mode on
00 HSYNC
01 nHSYNC
10 CSYNCnor
11 nCSYNCnor
00 VSYNC
01 nVSYNC
10 CSYNCxnor
11 nCSYNCxnor
This register contains the control bits for the external functions of the video and sound macrocell. In par-
ticular, it controls the DACs, the configuration of the External port, ED[7:0], and the configuration of the
sync lines. EREG[1:0] are mapped internally to drive esel[1:0] by CL-PS7500FE. EREG[7:4] are exported
from the chip on ED[7:4] if EREG[1:0] = 3. Refer to Chapter 12. The use of EREG[10:8] (pedon[2:0]) and
DAC is defined in Chapter 12.The use of EREG[13] (lcd) and EREG[14] (hrm) are defined in Chapter 12.
CL-PS7500FE can export a variety of sync configurations on the pins HSYNC and VSYNC, as specified
by the bits 16–17 and 18–19, respectively. For further explanation see Chapter 12.
June 1997
151
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
CIRRUS [ CIRRUS LOGIC ]
