CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.27 Control Register (CONREG): Address 0xE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 0
0 0 0 0
X X
X
X X X X X X X X X X X
Pixel source
Pixel rate
00VCLK
01 HCLK
10 RCLK
000 CK
001 CK/2
010 CK/3
011 CK/4
100 CK/5
101 CK/6
110 CK/7
111 CK/8
BITS/pixel
FIFO loads
000 1
001 2
010 4
011 8
100 16
101 N/S
110 32
111 N/S
000 N/S
001 4
010 8
011 12
100 16
101 20
110 24
111 28
INT (must be set to ‘0’)
DUP
Power down
Test must be set to ‘0000’
This main control register determines the basic operation of the CL-PS7500FE. The pixel clock source,
the pixel rate, the number of bits/pixel, the control of the video FIFO, and the data format are programmed
in this register. In addition, there is a 4-bit test register that must be programmed to ‘0’ for normal opera-
tion.
NOTE: The INT bit must always be set to ‘0’.
The pixel clock (PIXCLK) is selected from one of three sources, corresponding to the respective input
pins, and the selected clock is then fed through a prescalar as defined by the 3 bits CONREG[4:2]. The
output of this prescalar is the actual pixel clock. See Chapter 12 for more details.
The video FIFO can be programmed to have any number of qwords loaded into it at the start of display.
The value chosen should take into account the bandwidth of the display, as well as the latency of the DMA
subsystem. Refer to Chapter 15 before programming these values. When CONREG[13] (DUP) is set, the
display for dual-panel LCDs is configured. This is further described in Chapter 12.
NOTE: After a reset, CONREG must be the first register programmed. CONREG[14] must then be immediately be
programmed low.The test registers bits (19:16) should also be programmed low, as any other setting inhibits
normal operation.
The video macrocell uses dynamic logic structures for maximum performance.When CONREG[14] is set
high, the main video data path is set into a state where it does not consume static current. This must be
done before the CL-PS7500FE is set into STOP mode.
June 1997
153
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
CIRRUS [ CIRRUS LOGIC ]
