CL-PS7500FE
System-on-a-Chip for Internet Appliance
16.30 Sound Control Register (SCTL): Address 0xB1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 0 1 1 0 0 0 1
X X X X
sclr
sdac
dss
clksel
This 4-bit register defines various control bits for the sound system.
Bit 3: sclr
Bit 2: sdac
Bit 1: dss
Bit 0: clksel
This bit must always be programmed low.
This bit must be written as ‘0’.
This bit selects Serial Sound mode.
This bit selects the clock used in the sound system. When this bit is
high, the internal CL-PS7500FE 32-MHz I/O reference clock is used;
when low the optional sound clock is used.
June 1997
155
ADVANCE DATA BOOK v2.0
THE VIDEO SOUND AND PROGRAMMER’S MODEL
CIRRUS [ CIRRUS LOGIC ]
