欢迎访问ic37.com |
会员登录 免费注册
发布采购

CL-PS7500FE 参数 Datasheet PDF下载

CL-PS7500FE图片预览
型号: CL-PS7500FE
PDF下载: 下载PDF文件 查看货源
内容描述: 系统级芯片一个用于互联网设备 [System-on-a Chip for Internet Appliance]
分类和应用:
文件页数/大小: 251 页 / 2292 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CL-PS7500FE的Datasheet PDF文件第146页浏览型号CL-PS7500FE的Datasheet PDF文件第147页浏览型号CL-PS7500FE的Datasheet PDF文件第148页浏览型号CL-PS7500FE的Datasheet PDF文件第149页浏览型号CL-PS7500FE的Datasheet PDF文件第151页浏览型号CL-PS7500FE的Datasheet PDF文件第152页浏览型号CL-PS7500FE的Datasheet PDF文件第153页浏览型号CL-PS7500FE的Datasheet PDF文件第154页  
CL-PS7500FE  
System-on-a-Chip for Internet Appliance  
16.20 Vertical Display End Register (VDER): Address 0x94  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
1 0 0 1  
0 1 0 0  
X X X X X X X X X X X X X  
VDER value  
This 13-bit register defines the time, in units of a raster, from the start of the VSYNC pulse to the end of  
the video display. (that is, the first raster where the display is not present). If N rasters are required in this  
time, then program the value (N 1) into the VDER.  
16.21 Vertical Border End Register (VBER): Address 0x95  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
1 0 0 1  
0 1 0 1  
X X X X X X X X X X X X X  
VBER value  
This 13-bit register defines the time, in units of a raster, from the start of the VSYNC pulse to the end of  
the border display (that is, the first raster where the border is not present). If N rasters are required in this  
time, then program the value (N 1) into the VBER. If no border is required, then this register must be  
programmed to the same value as the VDER.  
16.22 Vertical Cursor Start Register (VCSR): Address 0x96  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
1 0 0 1  
0 1 1 0  
X X  
X X X X X X X X X X X X X  
VCSR value  
00 normal operation  
01 upper half-screen only  
10 lower half-screen only  
11 split screen  
This is a 15-bit register.The lower 13 bits define the time, in units of a raster, from the start of the VSYNC  
pulse to the start of the cursor display. If N rasters are required in this time, then program the value (N −  
1) into the VCSR. The upper 2 bits control the display of the cursor in duplex LCD mode. Program these  
bits to ‘0’ in all other modes.  
When the upper 2 bits are programmed to ‘11’ (split screen) the meaning of VCSR and VCER are altered  
as follows: The cursor is displayed in the lower half-screen only from the value of VDSR to the value of  
VCSR, and again in the upper half-screen only from the value of VCER to the value of VDER.This allows  
a cursor to be positioned across the boundary of the upper and lower half-screens of an LCD.  
June 1997  
149  
ADVANCE DATA BOOK v2.0  
THE VIDEO SOUND AND PROGRAMMER’S MODEL