Data Sheet
Table 7. LVDS Internal Termination Programmability
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
1
1
1
en_lvds_term
Enables internal termination for
LVDS buffers
Termination
disabled
X
X
X
term_lclk<2:0>
Programmable termination for
LCLKN and LCLKP buffers
Termination
disabled
12
X
X
X
term_
frame<2:0>
Programmable termination for
FCLKN and FCLKP buffers
Termination
disabled
X
X
X
term_dat<2:0>
Programmable termination for
DxP and DxN buffers
Termination
disabled
The off-chip load on the LVDS buffers may represent a characteristic impedance that is not perfectly matched with
the PCB traces. This may result in reflections back to the LVDS outputs and loss of signal integrity. This effect can be
mitigated by enabling an internal termination between the positive and negative outputs of each LVDS buffer. Internal
termination mode can be selected by setting the en_lvds_term bit to '1'. Once this bit is set, the internal termination
values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. Table
8 shows how the internal termination of the LVDS buffers are programmed. The values are typical values and can vary
by up to ±20% from device to device and across temperature.
Table 8. LVDS Output INternal Termination for LCLK, FCLK, and Data
term_*<2:0>
LVDS Internal Termination
000
001
010
011
100
101
110
111
Termination Disabled
280Ω
165Ω
100Ω
125Ω
82Ω
67Ω
56Ω
Table 9. Analog Input Invert
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
X
X
X
X
invert_ch<8:1>
Swaps the polarity of the analog IPx is positive
input pins electrically input
24
The IPx pin represents the positive analog input pin, and INx represents the negative (complementary) input. Setting
the bits marked invert_ch <8:1> (individual control for each channel) causes the inputs to be swapped. INx would then
represent the positive input, and IPx the negative input.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
20
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
