Data Sheet
Table 12. Gain Setting for Channels 1-8
gain_chx<3:0>
0000
Channel x Gain Setting
0dB
1dB
0001
0010
2dB
0011
3dB
0100
4dB
0101
5dB
0110
6dB
0111
7dB
1000
8dB
1001
9dB
1010
10dB
1011
11dB
1100
12dB
1101
Do not use
Do not use
Do not use
1110
1111
Table 13. LVDS Clock Programmability and Data Output Modes
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
phase_ddr<1:0>
btc_mode
Description
Default
Controls the phase of LCLK out-
put relative to data
X
X
90 degrees
42
Binary two's complement format Straight offset
for ADC output data
X
binary
Serialized ADC output data
comes out with MSB first
LSB-first
output
X
msb_first
Enable SDR output mode. LCLK
becomes a 12x input clock
DDR output
mode
X
1
en_sdr
46
Rising edge
of LCLK
comes in the
middle of the
data window
Controls whether the LCLK ris-
ing or falling edge comes in the
middle of the data window when
operating in SDR mode
X
fall_sdr
The output interface of CDK8307 is normally a DDR interface, with the LCLK rising and falling edge transitions in the
middle of alternate data windows. The phase for LCLK can be programmed relative to the output frame clock and data
using bits phase_ddr<1:0>. The LCLK phase modes are shown in Figure 6. The default timing is identical to setting
phase_ddr<1:0> = '10'.
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www.cadeka.com
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