Data Sheet
Serial Register Map
Table 2. Summary of Functions Supported by the Serial Interface
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Software reset.
This bit is self-clearing
Channel-specific power-down
Go to sleep-mode
Default
Inactive
X
X
rst
00
X
X
X
X
X
X
X
pd_ch<8:1>
sleep
Inactive
Inactive
Inactive
X
X
pd
Go to power-down
0F
PD pin
Configures the PD pin for
sleep-modes
configured for
power-down
mode
X
X
X
pd_pin_cfg<1:0>
ilvds_lclk<2:0>
LVDS current drive programma-
bility for LCLKP and LCLKN pins
X
X
X
3.5mA drive
3.5mA drive
3.5mA drive
ilvds_
frame<2:0>
LVDS current drive programma-
bility for FCLKP and FCLKN pins
X
X
X
11
12
LVDS current drive programma-
bility for output data pins
X
X
ilvds_dat<2:0>
en_lvds_term
Enables internal termination
for LVDS buffers
Termination
disabled
X
1
1
1
Programmable termination
for LCLKN and LCLKP buffers
Termination
disabled
X
X
X
X
X
X
term_lclk<2:0>
term_
frame<2:0>
Programmable termination
for FCLKN and FCLKP buffers
Termination
disabled
X
X
X
Programmable termination
for output data buffers
Termination
disabled
X
X
X
term_dat<2:0>
invert_ch<8:1>
en_ramp
Swaps the polarity of the
analog input pins electrically
IPx is
positive input
X
X
X
X
0
X
0
X
24
25
Enables a repeating full-scale
ramp pattern on the outputs
Inactive
Inactive
Inactive
Enable the mode wherein the
dual_custom_pat output toggles between two
defined codes
0
0
X
X
X
0
X
X
0
X
X
X
single_custom_
pat
Enables the mode wherein the
output is a constant specified code
Bits for the single custom pattern
and for the first code of the dual Inactive
custom pattern. <0> is the LSB
bits_cus-
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
26
27
tom1<13:0>
bits_cus-
tom2<13:0>
Bits for the second code of the
Inactive
X
X
X
X
dual custom pattern
X
X
gain_ch1<3:0>
gain_ch2<3:0>
gain_ch3<3:0>
gain_ch4<3:0>
gain_ch5<3:0>
gain_ch6<3:0>
gain_ch7<3:0>
gain_ch8<3:0>
Programmable gain for channel 1 0dB gain
Programmable gain for channel 2 0dB gain
Programmable gain for channel 3 0dB gain
Programmable gain for channel 4 0dB gain
Programmable gain for channel 5 0dB gain
Programmable gain for channel 6 0dB gain
Programmable gain for channel 7 0dB gain
Programmable gain for channel 8 0dB gain
X
X
X
X
2A
2B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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www.cadeka.com
17
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
