Data Sheet
Table 10. LVDS Test Patterns
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Inactive
X
0
0
X
0
X
0
X
0
0
X
X
en_ramp
Enables a repeating full-scale
ramp pattern on the outputs
dual_custom_pat Enable the mode wherein the output Inactive
toggles between two defined codes
25
26
single_custom_
pat
Enables the mode wherein the
output is a constant specified code
Inactive
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
bits_cus-
tom1<13:0>
Bits for the single custom pattern Inactive
and for the first code of the dual
custom pattern. <0> is the LSB
X
X
X
bits_cus-
tom2<13:0>
Bits for the second code of the
dual custom pattern
Inactive
27
45
0
X
X
0
pat_deskew
pat_sync
Enable deskew pattern mode
Enable sync pattern mode
Inactive
Inactive
To ease the LVDS synchronization setup of CDK8307, several test patterns can be set up on the outputs. Normal ADC
data are replaced by the test pattern in these modes. Setting en_ramp to '1' sets up a repeating full-scale ramp pattern
on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and
starts the ramp again after reaching the full-scale code.
A constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value
in bits_custom1<13:0>. In this mode, bits_custom1<13:0> replaces the ADC data at the output, and is controlled by
LSB-first and MSB-first modes in the same way as normal ADC data are.
The device may also be made to alternate between two codes by programming dual_custom_pat to '1'. The two codes
are the contents of bits_custom1<13:0> and bits_custom2<13:0>. Two preset patterns can also be selected:
1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with '01010101010101' (two LSBs
removed in 12 bit mode).
2. Sync pattern: Set using pat_sync, the normal ADC word is replaced by a fixed 1111110000000 word.
Note: Only one of the above patterns should be selected at the same time.
Table 11. Programmable Gain
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
gain_ch1<3:0>
gain_ch2<3:0>
gain_ch3<3:0>
gain_ch4<3:0>
gain_ch5<3:0>
gain_ch6<3:0>
gain_ch7<3:0>
gain_ch8<3:0>
Programmable gain for channel 1 0dB gain
Programmable gain for channel 2 0dB gain
Programmable gain for channel 3 0dB gain
Programmable gain for channel 4 0dB gain
Programmable gain for channel 5 0dB gain
Programmable gain for channel 6 0dB gain
Programmable gain for channel 7 0dB gain
Programmable gain for channel 8 0dB gain
X
X
X
X
2A
2B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CDK8307 includes a purely digital programmable gain option in addition to the Full-scale Control. The programmable
gain of each channel can be individually set using a set of four bits, indicated as gain_chn<3:0> for Channel x. The gain
setting is coded in binary from 0dB to 12dB, as shown in Table 12 on the following page.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
21
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
