Data Sheet
Table 2. Summary of Functions Supported by the Serial Interface (Continued)
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Controls the phase of LCLK
output relative to data
X
X
phase_ddr<1:0>
90 degrees
42
45
0
X
X
0
pat_deskew
pat_sync
Enable deskew pattern mode
Enable sync pattern mode
Inactive
Inactive
Binary two's complement
format for ADC output data
Straight
X
btc_mode
msb_first
en_sdr
offset binary
Serialized ADC output data
comes out with MSB first
LSB-first
output
X
Enable SDR output mode. LCLK
becomes a 12x input clock
DDR
output mode
X
1
46
Rising edge
of LCLK
comes in the
middle of the
data window
Controls whether the LCLK ris-
ing or falling edge comes in the
middle of the data window when
operating in SDR mode
X
fall_sdr
X
X
X
X
X
perfm_cntrl<2:0> ADC performance control
Nominal
50
52
X
0
X
ext_vcm_bc<1:0> VCM buffer driving strength control Nominal
lvds_pd_mode
Controls LVDS power down mode High z mode
Sets the number of LVDS
12-bit
lvds_num_bits
output bits
Advance LVDS data bits and
Inactive
X
lvds_advance
lvds_delay
53
frame clock by one clock cycle
Delay LVDS data bits and frame
Inactive
X
X
0
X
clock by one clock cycle
X
X
X
X
X
X
fs_cntrl<5:0>
clk_freq<1:0>
Fine adjust ADC full scale range 0% change
55
56
Input clock frequency
65MHz
Description of Serial Registers
Table 3. Software Reset
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Self-clearing software reset
Default
Inactive
X
rst
00
Setting the rst register bit to '1', resets all internal registers including the rst register bit itself.
Table 4. Power-Down Modes
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
Inactive
X
X
X
X
X
X
X
X
X
pd_ch<8:1>
sleep
Channel-specific power-down
Go to sleep-mode
X
Inactive
Inactive
X
pd
Go to power-down
0F
52
PD pin config-
ured for power-
down mode
Configures the PD pin for
sleep-mode
X
X
pd_pin_cfg<1:0>
lvds_pd_mode
Controls LVDS power down mode High z mode
©2009 CADEKA Microcircuits LLC
www.cadeka.com
18
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