Data Sheet
PHASE_DDR<1:0>=’00’ = 270°
PHASE_DDR<1:0>=’01’ =180°
FCLKN
FCLKN
FCLKP
LCLKP
LCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
Dxx<1:0>
PHASE_DDR<1:0>=’10’ = 90° (Default)
PHASE_DDR<1:0>=’11’ = 0°
FCLKN
FCLKN
FCLKP
LCLKN
LCLKP
FCLKP
LCLKP
LCLKN
Dxx<1:0>
Dxx<1:0>
Figure 6. Phase Programmability Modes for LCLK
The device can also be made to operate in SDR mode by setting the en_sdr bit to '1'. The bit clock (LCLK) is output at
12x times the input clock in this mode, two times the rate in DDR mode. Depending on the state of fall_sdr, LCLK may
be output in either of the two manners shown in Figure 7. As can be seen in Figure 7, only the LCLK rising (or falling)
edge is used to capture the output data in SDR mode. The SDR mode is not recommended beyond 40MSPS because the
LCLK frequency becomes very high.
EN_SDR=’1’, FALL_SDR_’0’
FCLKN
EN_SDR=’1’, FALL_SDR_’1’
FCLKN
FCLKP
LCLKP
LCLKN
FCLKP
LCLKN
LCLKP
Dxx<1:0>
Dxx<1:0>
Figure 7. SDR Interface Modes
The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to
'1' which inverts the MSB.
The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Program-
ming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge.
Table 14. Number of Serial Output Bits
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
lvds_num_bits
Sets the number if LVDS output bits 12-bit
Advance LVDS data bits and frame
clock by one clock cycle
0
X
X
0
lvds_advance
lvds_delay
Inactive
53
Delay LVDS data bits and frame
clock by one clock cycle
Inactive
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www.cadeka.com
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CADEKA [ CADEKA MICROCIRCUITS LLC. ]
