Data Sheet
The ADC channels have 13 bits of resolution. There are two options for the serial LVDS outputs, 12 bits or 14 bits, se-
lected by setting lvds_num_bits to '0' or '1', respectively. In 12-bit mode, the LSB bit from the ADCs are removed in the
output stream. In 14-bit mode, a '0' is added in the LSB position. Power down mode must be activated after or during
a change in the number of output bits.
To ease timing in the receiver when using multiple ADC chips, the CDK8307 has the option to adjust the timing of the
output data and the frame clock. The propagation delay with respect to the ADC input clock can be moved one LVDS
clock cycle forward or backward, by using lvds_advance and lvds_delay, respectively. See figure 8 for details. Note that
LCLK is not affected by lvds_delay or lvds_advance settings.
TLVDS
LCLKP
LCLKN
TPROP
FCLKP
default:
FCLKN
D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Dxx<1:0>
N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
N
N
N
N
N
N
N
TPROP
TLVDS
FCLKP
FCLKN
lvds_delay = ‘1’:
D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8
Dxx<1:0>
N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
N
N
N
N
N
N
TPROP
TLVDS
FCLKP
FCLKN
lvds_advance = ‘1’:
D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Dxx<1:0>
N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1
N
N
N
N
N
N
N
N
N
N
N
*LVDS output timing adjustment
Figure 8: LVDS Output Timing Adjustment
Table 15. Full Scale Control
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
X
X
X
fs_cntrl<5:0>
Fine adjust ADC full scale range 0% change
55
The full-scale voltage range of CDK8307 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register.
Changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. This leads to a maximum
range of ±10% adjustment. Table 16 shows how the register settings correspond to the full-scale range. Note that the
values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous.
The full-scale control and the programmable gain features differ in two major ways:
1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable
gain is a digital feature.
2. The programmable gain feature has much coarser gain steps and larger range than the full-scale control.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
24
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
