Data Sheet
Serial Interface
The CDK8307 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial
interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low:
nꢀ
Serial data are shifted into the chip
nꢀ
At every rising edge of SCLK, the value present at SDATA is latched
nꢀ
SDATA is loaded into the register every 24th rising edge of SCLK
Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into
SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is
divided into two parts:
nꢀ
The first eight bits form the register address
nꢀ
The remaining 16 bits form the register data
Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled.
Timing Diagram
Figure 5 shows the timing of the serial port interface. Table 1 explains the timing variables used in the Timing Diagram.
tcchhi
tcs
thi
tclk
ts
tch
i
tlo
th
CSN
SCLK
A7
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4 D3
D2
D1 D0
SDATA
Figure 5. Serial Port Interface Timing Diagram
Table 1. Serial Port Interface Timing Definitions
Parameter
Description
Minimum Value
Unit
t
Setup time between CSN and SCLK
Hold time between CSN and SCLK
SCLK high time
8
8
ns
ns
ns
ns
ns
ns
ns
cs
t
ch
t
20
20
50
5
hi
lo
t
SCLK low time
t
SCLK period
clk
t
Data setup time
s
t
Data hold time
5
h
Register Initialization
Before CDK8307 can be used, the internal registers must be initialized to their default values and power down must be
activated. This can be done immediately after applying supply voltage to the circuit. Register initialization can be done
in one of two ways:
1. By applying a low-going pulse (minimum 20ns) on the RESETN pin (asynchronous).
2. By using the serial interface to set the RST bit high. Internal registers are reset to default values when this bit is set.
The RST bit is self-reset to zero. When using this method, do not apply any low-going pulse on the RESETN pin.
Power down initialization can be done in one of two ways:
1. By applying a high-going pulse (minimum 20ns) on the PD pin (asynchronous).
2. By cycling the SPI register 0Fhex PD bit to high (reg value '0200'hex) and then low (reg value '0000'hex).
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www.cadeka.com
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