Data Sheet
Setting pd_ch<n> = '1', powers down channel <n> of the ADC. Setting sleep = '1', powers down the entire chip, except
the band-gap reference circuit.
Setting pd = '1' completely powers down the chip, including the band-gap reference circuit. Start-up time from this mode
is significantly longer than from the sleep and pd_ch<n> modes.
Setting pdn_pin_cfg = '1' configures the circuit to enter sleep mode when the PD pin is set high. When pdn_pin_cfg =
'0', which is the default, the circuit enters power down mode when the PD pin is set high.
The lvds_pd_mode register configures whether the LVDS data output drivers are powered down or not in sleep and
sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep
channel modes. If lvds_pd_mode is set low (default), the LVDS output is put in high Z, and the driver is completely
powered down. If lvds_pd_mode is set high, the LVDS output is set to constant 0, and the driver is still on during sleep
and sleep channel modes.
Table 5. LVDS Drive Strength Programmability
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Address
In Hex
Name
Description
Default
X
X
X
ilvds_lclk<2:0>
LVDS current drive programma- 3.5mA drive
bility for LCLKP and LCLKN pins.
X
X
X
ilvds_
frame<2:0>
LVDS current drive programma- 3.5mA drive
bility for FCLKP and FCLKN pins.
11
X
X
X
ilvds_dat<2:0>
LVDS current drive programma- 3.5mA drive
bility for output data pins.
The current delivered by the LVDS output drivers can be configured as shown in Table 6. The default current is 3.5mA,
which is what the LVDS standard specifies.
Setting the ilvds_lclk<2:0> register controls the current drive strength of the LVDS clock output on the LCLKP and LCLKN
pins.
Setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the FCLKP and
FCLKN pins.
Setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]
N pins.
Table 6. LVDS Output Drive Strength for LCLK, FCLK, and Data
ilvds_*<2:0>
LVDS Drive Strength
3.5 mA (default)
2.5 mA
000
001
010
011
100
101
110
111
1.5 mA
0.5 mA
7.5 mA
6.5 mA
5.5 mA
4.5 mA
©2009 CADEKA Microcircuits LLC
www.cadeka.com
19
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
