AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
t
RP
RASP
V
V
IH
IL
RAS
CAS
t
t
t
t
CSH
PC
CP
RSH
t
t
t
t
t
t
t
CP
CRP
RCD
CAS
CAS
CP
CAS
V
V
IH
IL
t
t
t
AR
ACH
t
t
t
t
RAD
ACH
ACH
RAL
CAH
t
t
t
t
t
t
t
ASC
ASR
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
t
t
t
t
t
CWL
CWL
WCH
WP
CWL
WCH
WP
t
t
t
t
t
WCS
WCS
WCH
WP
WCS
t
t
WRH
WRP
V
V
IH
IL
WE
NOTE 1
t
t
t
t
WCR
DHR
DH
RWL
t
t
t
t
t
DS
DS
DH
DS
DH
V
IOH
IOL
DQ
OE
VALID DATA
VALID DATA
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM
tACH
tAR
tASC
tASR
tCAH
tCAS
tCP
tCRP
tCSH
tCWL 15
tDH
tDHR
tDS
MIN
15
45
0
MAX
MIN
15
55
0
MAX
MIN
20
60
0
MAX UNITS
SYM
tRAD
tRAH
tRAL
MIN
15
MAX
MIN
15
MAX
MIN
15
MAX UNITS
ns
ns
ns
ns
ns
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
30
35
40
tRASP 60 100,000
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
70 100,000 80
100,00
60
0
0
0
10
12
15
16
40
13
15
10
40
0
45
16
50
15
15
12
50
0
50
20
60
15
20
15
60
0
12 10,000
15 10,000 20 10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
10
5
10
5
50
55
15
12
50
0
60
20
15
55
0
10
40
0
10
10
10
12
10
10
15
10
10
tWRH
tWRP
tPC
30
35
40
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-85
AUSTIN [ AUSTIN SEMICONDUCTOR ]
