AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
RAS-ONLY REFRESH CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
CAS
t
t
RPC
CRP
V
V
IH
IL
t
t
RAH
ASR
V
V
IH
IL
ADDR
ROW
ROW
V
OH
OL
DQ
WE
OPEN
V
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
NOTE 1
CBR REFRESH CYCLE
(Addresses and OE = DON’T CARE)
t
t
t
t
RAS
RP
RAS
RP
V
V
IH
IL
RAS
t
t
RPC
CP
t
t
t
RPC
t
t
CHR
CSR
CHR
CSR
V
V
IH
IL
CAS
DQ
V
V
OH
OL
OPEN
t
t
t
t
WRH
WRP
WRH
WRP
V
V
IH
IL
WE
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM
tASR
tCHR
tCP
tCRP
tCSR
tRAH
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX UNITS
SYM
tRAS
tRC
MIN
MAX
MIN
MAX
MIN
MAX UNITS
ns
ns
ns
ns
ns
ns
60 10,000 70 10,000 80 10,000
ns
ns
ns
ns
ns
ns
10
10
5
15
10
5
15
10
5
110
40
5
130
50
5
150
60
5
tRP
tRPC
tWRH
tWRP
5
5
10
10
10
10
10
10
10
10
10
10
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-89
AUSTIN [ AUSTIN SEMICONDUCTOR ]
