AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EARLY WRITE CYCLE
t
RC
t
t
RP
RAS
V
V
IH
IL
RAS
t
CSH
t
RSH
t
t
t
CRP
RCD
CAS
CAS
V
V
IH
IL
t
AR
t
t
t
t
RAD
RAH
RAL
CAH
t
t
ASC
ASR
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
CWL
t
t
t
t
RWL
WCR
WCH
WP
t
WCS
t
t
WRH
WRP
WE
V
V
IH
IL
NOTE 1
t
t
DHR
DH
t
DS
V
IOH
IOL
DQ
OE
VALID DATA
V
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM
tRAL
tRAS
tRC
tRCD
tRP
tRSH
tRWL
tWCH
tWCR
tWCS
tWP
MIN
30
60
110
16
40
13
15
10
40
0
MAX
MIN MAX
35
MIN
MAX UNITS
SYM
tACH
tAR
MIN
15
45
0
MAX
MIN
15
55
0
MAX
MIN
20
60
0
MAX UNITS
40
ns
ns
ns
ns
ns
ns
10,000
45
70 10,000 80 10,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tASC
tASR
tCAH
tCAS
tCRP
tCSH
tCWL
tDH
tDHR
tDS
tRAD
tRAH
130
16
50
15
15
12
50
0
150
20
60
0
50
60
0
0
0
10
15
15
12 10,000 15
10,000
20 10,000 ns
20
15
60
0
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
50
15
10
40
0
55
15
12
50
0
60
20
15
55
0
10
10
10
12
10
10
15
10
10
tWRH
tWRP
15
10
30
15
10
35
15
10
40
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-82
AUSTIN [ AUSTIN SEMICONDUCTOR ]
