AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
t
RASP
RP
V
V
IH
IL
RAS
t
t
t
t
t
NOTE 1
CSH
PC
PRWC
RSH
CAS
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CP
V
V
IH
IL
CAS
t
AR
t
t
t
RAL
RAD
RAH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
ROW
COLUMN
COLUMN
COLUMN
ROW
t
RWD
t
RWL
t
RCS
t
t
t
CWL
CWL
CWL
t
t
t
WP
WP
WP
t
t
t
t
AWD
AWD
AWD
CWD
t
t
WRH
t
t
WRP
CWD
CWD
V
V
IH
IL
WE
NOTE 2
t
t
t
AA
AA
AA
t
RAC
t
t
t
DH
DH
DH
t
t
CPA
CPA
t
t
t
DS
DS
DS
t
t
t
t
t
t
CAC
CLZ
CAC
CLZ
CAC
CLZ
V
IOH
IOL
VALID
OUT
VALID
IN
VALID
OUT
VALID
IN
VALID
OUT
VALID
D
DQ
OE
OPEN
OPEN
V
D
D
D
D
D
IN
t
t
t
OD
OD
OD
t
t
t
t
OE
OE
OE
OEH
V
V
IH
IL
DON’T CARE
UNDEFINED
t
NOTE:
1. PC is for LATE WRITE cycles only.
2. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM
tAA
tAR
MIN
MAX
MIN MAX
MIN MAX UNITS
SYM
tOE
tOEH
MIN
MAX
MIN MAX
MIN MAX UNITS
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
0
55
60
0
10
30
12
35
85
70
15
40
90
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCLZ
tCP
tCPA
tCRP
tCSH
tCWD
tCWL
tDH
0
tPC
t
0
0
0
PRWC 75
tRAC
55
65
65
60
30
80
40
tRAD
tRAH
tRAL
15
10
30
15
10
35
35
15
10
40
15
20
20
10
15
15
12 10,000
15 10,000
20 10,000
tRASP 60 100,000
70 100,000
80 100,000
0
0
0
tRCD
tRCS
tRP
tRSH
tRWD
tRWL
tWP
16
0
45
16
0
50
20
0
60
10
35
5
10
40
5
10
40
5
40
13
80
15
10
10
10
50
15
90
15
12
10
10
60
15
105
20
15
10
10
50
35
15
10
0
55
40
15
12
0
60
45
20
15
0
tDS
tOD
tWRH
tWRP
0
15
0
15
0
20
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-86
AUSTIN [ AUSTIN SEMICONDUCTOR ]
