AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODEREAD-EARLY-WRITECYCLE
(Pseudo READ-MODIFY-WRITE)
t
t
RP
RASP
V
V
IH
IL
RAS
t
CSH
t
t
t
PC
RSH
PC
t
t
t
t
t
t
t
t
CRP
RCD
CAS
CP
CAS
CP
CAS
CP
V
V
IH
IL
CAS
t
t
t
RAL
AR
t
t
t
RAD
ACH
CAH
t
ASR
t
t
t
t
t
ASC
RAH
ASC
CAH
ASC
CAH
V
V
IH
IL
ADDR
WE
ROW
t
COLUMN (A)
COLUMN (B)
ROW
COLUMN (N)
t
t
RCH
t
t
t
t
WRP
WRH
RCS
WCS
WCH
V
V
IH
IL
t
AA
t
t
NOTE 1
AA
t
CPA
RAC
t
t
DH
t
CAC
DS
CAC
t
t
WHZ
COH
V
V
IOH
IOL
VALID
DATA (B)
DQ
OE
VALID DATA
IN
OPEN
VALID DATA (A)
t
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
MAX
-7
-8
SYM
tAA
MIN
MAX
MIN
MAX
MIN
MAX UNITS
SYM
tPC
MIN
MIN
MAX
MIN
MAX UNITS
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
35
40
ns
tACH
tAR
15
45
0
15
55
0
20
60
0
tRAC
tRAD
tRAH
tRAL
60
30
70
35
80
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
10
30
15
10
35
15
10
40
tASC
tASR
tCAC
tCAH
tCAS
tCOH
tCP
tCPA
tCRP
tCSH
tDH
0
0
0
15
20
20
tRASP 60 100,000
70 100,000 80 100,000
10
15
15
tRCD
tRCH
tRCS
tRP
tRSH
tWCH
tWCS
tWHZ
tWRH
tWRP
16
0
45
16
0
50
20
0
60
12 10,000
15 10,000 20 10,000
5
5
5
0
0
0
10
35
5
10
10
40
13
10
0
50
15
12
0
60
15
15
0
40
20
40
20
5
55
12
0
5
60
15
0
50
10
0
0
13
0
15
0
15
tDS
tOE
10
10
10
10
10
10
15
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-87
AUSTIN [ AUSTIN SEMICONDUCTOR ]
