AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
EDO-PAGE-MODE READ CYCLE
t
t
RASP
RP
V
V
IH
IL
RAS
CAS
t
t
t
t
RSH
CSH
PC
CP
t
t
t
t
t
t
t
CRP
RCD
CAS
CAS
CP
CAS
CP
V
V
IH
IL
t
t
RAL
AR
t
t
t
t
t
ACH
ACH
RAD
RAH
ACH
t
t
t
t
t
t
t
CAH
ASR
ASC
CAH
ASC
CAH
ASC
V
V
IH
IL
ADDR
WE
ROW
COLUMN
COLUMN
COLUMN
ROW
t
t
WRH
t
WRP
RCS
t
RCH
V
V
IH
IL
t
t
t
t
RRH
AA
NOTE 1
t
t
t
t
AA
AA
CPA
CAC
t
RAC
CPA
CAC
t
t
CAC
CLZ
t
OEHC
t
OFF
t
COH
t
CLZ
V
OH
OL
VALID
DATA
VALID
DATA
VALID
DATA
DQ
OE
OPEN
OPEN
V
t
t
t
OE
OE
t
OD
OD
t
OES
t
V
V
OES
IH
IL
t
OEP
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
MIN
-7
-8
MIN
SYM
tAA
tACH
tAR
MIN
MAX
MIN
MAX
MIN
MAX UNITS
SYM
tOEP
tOES
tOFF
tPC
tRAC
tRAD
tRAH
tRAL
tRASP
tRCD
tRCH
tRCS
tRP
MAX
MIN
10
5
MAX
MAX UNITS
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
10
5
ns
ns
15
45
0
15
55
0
20
60
0
0
15
0
15
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCOH
tCP
tCPA
tCRP
tCSH
tOD
30
35
40
0
0
0
60
30
70
35
80
40
15
20
20
15
10
30
15
10
35
15
10
40
10
15
15
12 10,000
15 10,000 20 10,000
0
5
0
5
0
5
60 100,000
70 100,000 80 100,000
16
0
45
16
0
50
20
0
60
10
35
5
10
10
40
40
0
0
0
5
55
0
5
60
0
40
0
50
0
60
0
50
tRRH
tRSH
tWRH
tWRP
0
15
15
15
20
20
20
13
10
10
15
10
10
15
10
10
tOE
tOEHC 10
10
10
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-84
AUSTIN [ AUSTIN SEMICONDUCTOR ]
