AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
READ CYCLE
tRC
tRAS
V IH
V IL
tCSH
tRSH
tCRP
CAS
V IH
V IL
tRCD
tCAS
tRRH
tRP
RAS
ADDR
WE
DQ
OE
NOTE:
1. Although
?
W
/
E is a “don’t care” at
?
R
?
A
/
S time during an access cycle (READ or WRITE), the system designer should implement
?
W
/
E HIGH for
t
WRP and
t
WRH. This design implementation will facilitate compatibility with future EDO DRAMs.
2.
t
OFF is referenced from rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
, ,,, ,,,,, ,
,,,,, , , ,, ,
,, ,
, ,
,,,,,,,,,,
,,
,,,,,,
, ,
, ,
,,
,
tAR
tRAD
tRAH
tRAL
tASR
tASC
tCAH
tACH
V IH
V IL
ROW
COLUMN
ROW
tWRP
tWRH
tRCS
tRCH
V IH
V IL
NOTE 1
tAA
tRAC
tCAC
tCLZ
NOTE 2
tOFF
V OH
V OL
OPEN
VALID DATA
OPEN
t OE
t OD
V IH
V IL
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-6
SYM
t
AA
t
ACH
t
AR
t
ASC
t
ASR
t
CAC
t
CAH
t
CAS
t
CLZ
t
CRP
t
CSH
t
OD
t
OE
t
OFF
AS4LC4M4
Rev. 11/97
DS000022
-7
MAX
30
MIN
15
50
0
0
15
20
15
15
0
5
55
0
0
10,000
15
20
0
5
60
MAX
35
MIN
20
60
0
0
-8
MAX
40
UNITS
-6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM
t
RAC
t
RAD
t
RAH
t
RAL
t
RAS
t
RC
t
RCD
t
RCH
t
RCS
t
RP
t
RRH
t
RSH
t
WRH
t
WRP
MIN
15
10
30
60
110
16
0
0
40
0
10
10
10
MAX
60
30
MIN
15
10
35
70
130
16
0
0
50
0
12
10
10
-7
MAX
70
35
MIN
15
10
40
80
150
20
0
0
60
0
15
10
10
-8
MAX
80
40
UNITS
MIN
15
45
0
0
10
12
0
5
50
0
0
10,000
45
10,000
50
10,000
60
20
10,000
10,000
15
15
15
15
20
15
0
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-81
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN [ AUSTIN SEMICONDUCTOR ]
