AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
t
RWC
t
t
RAS
RP
V
IH
RAS
CAS
V
IL
t
CSH
t
RSH
t
t
t
t
CAS
CRP
RCD
V
V
IH
IL
t
AR
t
t
RAL
RAD
t
t
t
t
ASC
RCS
CAH
ASR
RAH
t
ACH
V
V
IH
IL
ADDR
ROW
COLUMN
ROW
t
t
t
t
RWD
CWL
RWL
WP
t
CWD
t
t
t
WRH
AWD
WRP
V
V
IH
IL
WE
NOTE 1
t
AA
t
RAC
t
CAC
t
t
DS
DH
t
CLZ
V
IOH
IOL
VALID D
VALID D
DQ
OE
OPEN
OPEN
V
OUT
IN
t
t
t
OE
OD
OEH
V
V
IH
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
MIN
-7
-8
-6
-7
-8
SYM
tAA
tACH
tAR
tASC
tASR
tAWD 55
tCAC
tCAH
tCAS
tCLZ
tCRP
tCSH
tCWD 35
tCWL
tDH
MAX
MIN MAX
MIN
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYM MIN
MAX
MIN
MAX
MIN
MAX UNITS
30
35
40
tOE
15
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
45
0
15
55
0
20
60
0
tOEH
tRAC
tRAD
tRAH
tRAL
tRAS
tRCD
tRCS
tRP
tRSH
tRWC 150
tRWD 80
tRWL
tWP
tWRH 10
tWRP 10
10
12
15
60
30
70
35
80
40
15
10
30
15
10
35
15
10
40
0
0
0
65
20
15
65
15
20
60 10,000
70 10,000 80 10,000
10
15
16
0
45
16
0
50
20
0
60
12 10,000
15 10,000 20 10,000
0
5
0
5
0
5
40
50
15
180
90
15
12
10
10
60
15
200
105
20
15
10
10
13
50
55
40
15
12
0
60
45
20
15
0
15
10
0
15
10
tDS
tOD
0
15
0
15
0
20
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-83
AUSTIN [ AUSTIN SEMICONDUCTOR ]
