AS4LC4M4 883C
4 MEG x 4 DRAM
AUSTIN SEMICONDUCTOR, INC.
READ CYCLE
(with WE-controlled disable)
V
V
IH
RAS
CAS
IL
t
t
CSH
CAS
t
t
t
RCD
CRP
CP
V
V
IH
IL
t
AR
t
t
RAD
RAH
t
t
t
t
ASC
ASR
ASC
CAH
V
V
IH
IL
ROW
t
COLUMN
COLUMN
ADDR
WE
t
t
WRP
WRH
RCS
t
t
t
RCH
WPZ
RCS
V
V
IH
IL
NOTE 1
t
t
t
t
AA
RAC
CAC
CLZ
t
t
WHZ
CLZ
V
V
OH
OL
DQ
OE
OPEN
OPEN
VALID DATA
t
t
OD
OE
V
IH
V
IL
DON’T CARE
UNDEFINED
NOTE:
1. Although WE is a “don’t care” at RAS time during an access cycle (READ or WRITE), the system designer should implement
WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with future EDO DRAMs.
TIMING PARAMETERS
-6
-7
-8
-6
-7
-8
SYM
tAA
tAR
MIN
MAX
MIN MAX
MIN
MAX UNITS
SYM
tOE
MIN
MAX
15
MIN MAX
MIN
MAX UNITS
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
70
20
80
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAC
tRAD
tRAH
tRCD
tRCH
tRCS
tWHZ
tWPZ
tWRH
tWRP
60
45
0
55
0
60
0
tASC
tASR
tCAC
tCAH
tCAS
tCLZ
tCP
tCRP
tCSH
tOD
15
10
16
0
30
15
10
16
0
35
15
10
20
0
0
0
0
15
20
15
20
45
14
50
60
20
10
12
0
15
10,000
15 10,000 20 10,000
0
0
0
0
10
5
0
10
5
0
0
16
0
10
5
10
10
10
12
10
10
15
10
10
50
0
55
0
60
0
15
15
20
AS4LC4M4
Rev. 11/97
DS000022
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
2-88
AUSTIN [ AUSTIN SEMICONDUCTOR ]
