AUSTIN SEMICONDUCTOR, INC.
AS4LC4M4 883C
4 MEG x 4 DRAM
NOTES
1.
2.
3.
4.
All voltages referenced to V
SS
.
This parameter is sampled. V
CC
= +3.3V; f = 1 MHz.
I
CC
is dependent on cycle rates.
I
CC
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the ful
temperature range is assured.
7. An initail pause of 100µs is required after power-up
followed by eight
/
R
/
A
/
S refresh cycles (/R
/
A
/
S ONLY or
CBR with
/
W
/
E HIGH) before proper device operation
is assured. The eight
/
R
/
A
/
S cycle wake-ups should be
repeated any thime the
t
REF refresh requirement is
exceeded.
8. AC characteristics assume
t
T = 2.5ns.
9. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
10. In addition to meeting the transition rate specifica-
tion, all input signals must transit between V
IH
and
V
IL
(or between V
IL
and V
IH
) in a monotonic manner.
11. Column address changed once each cycle.
12. Measured with a load equivalent to two TTL gates,
100pF and V
OL
= 0.8V and V
OH
= 2.0V.
13. Assumes that
t
RCD <
t
RCD (MAX). If
t
RCD is greater
than the maximum recommended value shown in this
table,
t
RAC will increase by the amount that
t
RCD
exceeds the value shown.
14. Assumes that
t
RCD≥
t
RCD (MAX).
15. If
?
C
?
A
/
S is LOW at the falling edge of
?
R
?
A
/
S, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer,
?
C
?
A
/
S must be
pulsed HIGH for
t
CP.
16. Operation within the
t
RCD (MAX) limit ensures that
t
RAC (MAX) can be met.
t
RCD (MAX) is specified as
a reference point only; if
t
RCD is greater than the
specified
t
RCD (MAX) limit, then access time is
controlled exclusively by
t
CAC, provided
t
RAD is not
exceeded.
17. Operation within the
t
RAD (MAX) limit ensures that
t
RAC (MIN) and
t
CAC (MIN) can be met.
t
RAD
(MAX) is specified as a reference point only; if
t
RAD
is greater than the specified
t
RAD (MAX) limit, then
access time is controlled exclusively by
t
AA, provided
t
RCD is not exceeded.
18. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
19.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to V
OH
or V
OL
. It is referenced from the
rising edge of
?
R
?
A
/
S or
?
C
?
A
/
S, whichever occurs last.
20. t
WCS,
t
RWD,
t
AWD and
t
CWD are not restrictive
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
≥
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If
t
WCS <
t
WCS (MIN) and
t
RWD
≥
t
RWD (MIN),
t
AWD
≥
t
AWD (MIN) and
t
CWD
≥
t
CWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate.
?
O
/
E held HIGH
and
?
W
/
E taken LOW after
?
C
?
A
/
S goes LOW results in a
LATE WRITE (?O
/
E-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD are not applicable in a LATE
WRITE cycle.
21. These parameters are referenced to
?
C
?
A
/
S leading edge
in EARLY WRITE cycles and
?
W
/
E leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
22. If
?
O
/
E is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally,
?
W
/
E
must be pulsed during
?
C
?
A
/
S HIGH time in order to
place I/O buffers in High-Z.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case,
?
W
/
E = LOW and
?
O
/
E = HIGH.
24.
t
WTS and
t
WTH are setup and hold specifications for
the
/
W
/
E pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of
t
WRP and
t
WRH in the
CBR REFRESH cycle.
AS4LC4M4
Rev. 11/97
DS000022
2-80
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
AUSTIN [ AUSTIN SEMICONDUCTOR ]
