ATmega64A
Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PE3/AIN1/OC3A
PE2/AIN0/XCK0
PE1/PDO/TXD0
PE0/PDI/RXD0
0
0
TXEN0
RXEN0
0
0
0
PORTE0 • PUD
0
0
TXEN0
RXEN0
0
0
1
0
OC3B ENABLE
UMSEL0
XCK0 OUTPUT
0
TXEN0
0
OC3B
TXD0
0
0
0
0
–
–
0
0
0
0
0
XCK0 INPUT
AIN0 INPUT
RXD0
–
AIO
AIN1 INPUT
13.3.6
Alternate Functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 13-18. If
some Port F pins are configured as outputs, it is essential that these do not switch when a con-
version is in progress. This might corrupt the result of the conversion. In ATmega103
compatibility mode Port F is input only. If the JTAG interface is enabled, the pull-up resistors on
pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
Table 13-18. Port F Pins Alternate Functions
Port Pin
PF7
Alternate Function
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
ADC4/TCK (ADC input channel 4 or JTAG Test Clock)
ADC3 (ADC input channel 3)
PF6
PF5
PF4
PF3
PF2
ADC2 (ADC input channel 2)
PF1
ADC1 (ADC input channel 1)
PF0
ADC0 (ADC input channel 0)
• TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-
ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
85
8160C–AVR–07/09
ATMEL [ ATMEL ]
