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ATMEGA64A-AU 参数 Datasheet PDF下载

ATMEGA64A-AU图片预览
型号: ATMEGA64A-AU
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,带有64K字节的系统内可编程闪存 [8-bit Microcontroller with 64K Bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 7964 K
品牌: ATMEL [ ATMEL ]
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ATmega64A  
• INT3/TXD1 – Port D, Bit 3  
INT3, External Interrupt Source 3: The PD3 pin can serve as an External Interrupt source to the  
MCU.  
TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is  
enabled, this pin is configured as an output regardless of the value of DDD3.  
• INT2/RXD1 – Port D, Bit 2  
INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the  
MCU.  
RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled  
this pin is configured as an input regardless of the value of DDD2. When the USART forces this  
pin to be an input, the pull-up can still be controlled by the PORTD2 bit.  
• INT1/SDA – Port D, Bit 1  
INT1, External Interrupt Source 1. The PD1 pin can serve as an External Interrupt source to the  
MCU.  
SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the  
Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the serial data I/O  
pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress  
spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with  
slew-rate limitation.  
• INT0/SCL – Port D, Bit 0  
INT0, External Interrupt Source 0. The PD0 pin can serve as an External Interrupt source to the  
MCU.  
SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the  
Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the serial clock  
I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup-  
press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver  
with slew-rate limitation.  
Table 13-13 and Table 13-14 relates the alternate functions of Port D to the overriding signals  
shown in Figure 13-5 on page 73.  
81  
8160C–AVR–07/09  
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