ATmega64A
• AIN0/XCK0 – Port E, Bit 2
AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
XCK0, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock
is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0
operates in synchronous mode.
• PDO/TXD0 – Port E, Bit 1
PDO, SPI Serial Programming Data output. During Serial Program Downloading, this pin is used
as data output line for the ATmega64A.
TXD0, UART0 Transmit Pin.
• PDI/RXD0 – Port E, Bit 0
PDI, SPI Serial Programming Data input. During serial program downloading, this pin is used as
data input line for the ATmega64A.
RXD0, USART0 Receive pin. Receive Data (Data Input pin for the USART0). When the
USART0 Receiver is enabled this pin is configured as an input regardless of the value of
DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on
the internal pull-up.
Table 13-16 and Table 13-17 relates the alternate functions of Port E to the overriding signals
shown in Figure 13-5 on page 73.
Table 13-16. Overriding Signals for Alternate Functions PE7:PE4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PE7/INT7/ICP3
PE6/INT6/T3
PE5/INT5/OC3C
PE4/INT4/OC3B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC3C ENABLE
OC3C
OC3B ENABLE
OC3B
0
0
INT7 ENABLE
1
INT6 ENABLE
1
INT5 ENABLE
1
INT4 ENABLE
1
INT7 INPUT/ICP3
INPUT
INT7 INPUT/T3
INPUT
INT5 INPUT
INT4 INPUT
AIO
–
–
–
–
84
8160C–AVR–07/09
ATMEL [ ATMEL ]
