ATmega64A
• WR – Port G, Bit 0
WR is the external data memory write control strobe.
Table 13-22 and Table 13-23 relates the alternate functions of Port G to the overriding signals
shown in Figure 13-5 on page 73.
Table 13-22. Overriding Signals for Alternate Functions in PG4:PG1
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PG4/TOSC1
PG3/TOSC2
PG2/ALE
PG1/RD
AS0
AS0
SRE
0
SRE
0
0
0
AS0
AS0
SRE
1
SRE
1
0
0
0
0
SRE
ALE
0
SRE
RD
0
0
0
AS0
AS0
0
0
0
0
–
–
–
–
AIO
T/C0 OSC INPUT
T/C0 OSC OUTPUT
–
–
Table 13-23. Overriding Signals for Alternate Functions in PG0
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PG0/WR
SRE
0
SRE
1
SRE
WR
0
0
–
AIO
–
13.4 Register Description
13.4.1
PORTA – Port A Data Register
Bit
7
PORTA7
R/W
0
6
PORTA6
R/W
0
5
PORTA5
R/W
0
4
PORTA4
R/W
0
3
PORTA3
R/W
0
2
PORTA2
R/W
0
1
PORTA1
R/W
0
0
PORTA0
R/W
0
PORTA
0x1B (0x3B)
Read/Write
Initial Value
88
8160C–AVR–07/09
ATMEL [ ATMEL ]
