ATmega64A
Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PF3/ADC3
PF2/ADC2
PF1/ADC1
PF0/ADC0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
13.3.7
Alternate Functions of Port G
In ATmega103 compatibility mode, only the alternate functions are the defaults for Port G, and
Port G cannot be used as General Digital Port Pins. The alternate pin configuration is as follows:
Table 13-21. Port G Pins Alternate Functions
Port Pin
PG4
Alternate Function
TOSC1 (RTC Oscillator Timer/Counter0)
TOSC2 (RTC Oscillator Timer/Counter0)
ALE (Address Latch Enable to external memory)
RD (Read strobe to external memory)
WR (Write strobe to external memory)
PG3
PG2
PG1
PG0
• TOSC1 – Port G, Bit 4
TOSC2, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting
output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and
the pin can not be used as an I/O pin.
• TOSC2 – Port G, Bit 3
TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous
clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the
inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the
pin cannot be used as an I/O pin.
• ALE – Port G, Bit 2
ALE is the external data memory Address Latch Enable signal.
• RD – Port G, Bit 1
RD is the external data memory read control strobe.
87
8160C–AVR–07/09
ATMEL [ ATMEL ]
