ATmega64A
13.4.2
13.4.3
13.4.4
13.4.5
13.4.6
13.4.7
13.4.8
13.4.9
DDRA – Port A Data Direction Register
Bit
7
DDA7
R/W
0
6
DDA6
R/W
0
5
DDA5
R/W
0
4
DDA4
R/W
0
3
DDA3
R/W
0
2
DDA2
R/W
0
1
0
0x1A (0x3A)
Read/Write
Initial Value
DDA1
R/W
0
DDA0
R/W
0
DDRA
PINA – Port A Input Pins Address
Bit
7
PINA7
R
6
PINA6
R
5
PINA5
R
4
PINA4
R
3
PINA3
R
2
PINA2
R
1
PINA1
R
0
PINA0
R
0x19 (0x39)
Read/Write
Initial Value
PINA
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PORTB – Port B Data Register
Bit
7
PORTB7
R/W
0
6
PORTB6
R/W
0
5
PORTB5
R/W
0
4
PORTB4
R/W
0
3
PORTB3
R/W
0
2
PORTB2
R/W
0
1
PORTB1
R/W
0
0
PORTB0
R/W
0
PORTB
DDRB
PINB
0x18 (0x38)
Read/Write
Initial Value
DDRB – Port B Data Direction Register
Bit
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
4
DDB4
R/W
0
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
0x17 (0x37)
Read/Write
Initial Value
PINB – Port B Input Pins Address
Bit
7
PINB7
R
6
PINB6
R
5
PINB5
R
4
PINB4
R
3
PINB3
R
2
PINB2
R
1
PINB1
R
0
PINB0
R
0x16 (0x36)
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PORTC – Port C Data Register
Bit
7
PORTC7
R/W
0
6
PORTC6
R/W
0
5
PORTC5
R/W
0
4
PORTC4
R/W
0
3
PORTC3
R/W
0
2
PORTC2
R/W
0
1
PORTC1
R/W
0
0
PORTC0
R/W
0
PORTC
DDRC
PINC
0x15 (0x35)
Read/Write
Initial Value
DDRC – Port C Data Direction Register
Bit
7
DDC7
R/W
0
6
DDC6
R/W
0
5
DDC5
R/W
0
4
DDC4
R/W
0
3
DDC3
R/W
0
2
DDC2
R/W
0
1
DDC1
R/W
0
0
DDC0
R/W
0
0x14 (0x34)
Read/Write
Initial Value
PINC – Port C Input Pins Address
Bit
7
PINC7
R
6
PINC6
R
5
PINC5
R
4
PINC4
R
3
PINC3
R
2
PINC2
R
1
PINC1
R
0
PINC0
R
0x13 (0x33)
Read/Write
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
In ATmega103 compatibility mode, DDRC and PINC Registers are initialized to being Push-pull
Zero Output. The port pins assumes their Initial Value, even if the clock is not running. Note that
89
8160C–AVR–07/09
ATMEL [ ATMEL ]
