ATmega64A
Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0(1)
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PC3/A11
PC2/A10
PC1/A9
PC0/A8
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
0
0
0
0
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
1
1
1
1
SRE • (XMM<5)
SRE • (XMM<6)
SRE • (XMM<7)
SRE • (XMM<7)
A11
0
A10
0
A9
0
A8
0
0
0
0
0
–
–
–
–
AIO
–
–
–
–
Note:
1. XMM = 0 in ATmega103 compatibility mode.
13.3.4
Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 13-12.
Table 13-12. Port D Pins Alternate Functions
Port Pin
PD7
Alternate Function
T2 (Timer/Counter2 Clock Input)
PD6
T1 (Timer/Counter1 Clock Input)
PD5
XCK1(1) (USART1 External Clock Input/Output)
PD4
ICP1 (Timer/Counter1 Input Capture Pin)
PD3
INT3/TXD1(1) (External Interrupt3 Input or UART1 Transmit Pin)
INT2/RXD1(1) (External Interrupt2 Input or UART1 Receive Pin)
INT1/SDA(1) (External Interrupt1 Input or TWI Serial DAta)
INT0/SCL(1) (External Interrupt0 Input or TWI Serial CLock)
PD2
PD1
PD0
Note:
1. XCK1, TXD1, RXD1, SDA, and SCL not applicable in ATmega103 compatibility mode.
The alternate pin configuration is as follows:
• T2 – Port D, Bit 7
T2, Timer/Counter2 Counter Source.
• T1 – Port D, Bit 6
T1, Timer/Counter1 Counter Source.
• XCK1 – Port D, Bit 5
XCK1, USART1 External Clock. The Data Direction Register (DDD5) controls whether the clock
is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1
operates in synchronous mode.
• ICP1 – Port D, Bit 4
ICP1 – Input Capture Pin1: The PD4 pin can act as an Input Capture pin for Timer/Counter1.
80
8160C–AVR–07/09
ATMEL [ ATMEL ]
