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895132-UL 参数 Datasheet PDF下载

895132-UL图片预览
型号: 895132-UL
PDF下载: 下载PDF文件 查看货源
内容描述: USB微控制器,带有64K字节Flash存储器 [USB Microcontroller with 64K Bytes Flash Memory]
分类和应用: 存储微控制器
文件页数/大小: 182 页 / 1660 K
品牌: ATMEL [ ATMEL ]
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Bit  
Bit  
Number  
Mnemonic Description  
Endpoint Enable Bit  
Set to enable the endpoint according to the device configuration. Endpoint 0 shall  
always be enabled after a hardware or USB bus reset and participate in the  
device configuration.  
7
EPEN  
Clear to disable the endpoint according to the device configuration.  
Reserved  
The values read from this bit is always 0. Do not set this bit.  
6 - 4  
-
Data Toggle Status Bit (Read-only)  
Set by hardware when a DATA1 packet is received.  
Cleared by hardware when a DATA0 packet is received.  
Note: When a new data packet is received without DTGL toggling from 1 to 0 or 0  
to 1, a packet may have been lost. When this occurs for a Bulk endpoint, the  
device firmware shall consider the host has retried transmitting a properly  
received packet because the host has not received a valid ACK, then the  
firmware shall discard the new packet (N.B. The endpoint resets to DATA0 only  
upon configuration).  
3
DTGL  
For interrupt endpoints, data toggling is managed as for Bulk endpoints when  
used.  
For Control endpoints, each SETUP transaction starts with a DATA0 and data  
toggling is then used as for Bulk endpoints until the end of the Data stage (for a  
control write transfer); the Status stage completes the data transfer with a DATA1  
(for a control read transfer).  
For Isochronous endpoints, the device firmware shall retrieve every new data  
packet and may ignore this bit.  
Endpoint Direction Bit  
Set to configure IN direction for Bulk, Interrupt and Isochronous endpoints.  
Clear to configure OUT direction for Bulk, Interrupt and Isochronous endpoints.  
This bit has no effect for Control endpoints.  
2
EPDIR  
Endpoint Type Bits  
Set this field according to the endpoint configuration (Endpoint 0 shall always be  
configured as Control):  
EPTYPE1:  
0
1 - 0  
0
0
1
1
0
1
0
1
Control endpoint  
Isochronous endpoint  
Bulk endpoint  
Interrupt endpoint  
Reset Value = 0000 0000b  
Table 62. UEPSTAX Register  
UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM)  
7
6
-
5
4
3
2
1
0
DIR  
STALLRQ  
TXRDY  
STLCRC  
RXSETUP  
RXOUT  
TXCMP  
76  
AT89C5132  
4173E–USB–09/07  
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