Bit
Bit
Number
Mnemonic Description
Reserved
The values read from these Bits are always 0. Do not set these Bits.
7 - 4
-
Endpoint 3 FIFO Reset
EP3RST Set and clear to reset the endpoint 3 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
3
Endpoint 2 FIFO Reset
EP2RST Set and clear to reset the endpoint 2 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
2
1
0
Endpoint 1 FIFO Reset
EP1RST Set and clear to reset the endpoint 1 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Endpoint 0 FIFO Reset
EP0RST Set and clear to reset the endpoint 0 FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Reset Value = 0000 0000b
Table 64. UEPINT Register
UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3INT
EP2INT
EP1INT
EP0INT
Bit
Bit
Number
Mnemonic Description
Reserved
The values read from these Bits are always 0. Do not set these Bits.
7 - 4
-
Endpoint 3 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 3
interrupt is enabled in UEPIEN.
Must be cleared by software.
3
EP3INT
EP2INT
EP1INT
EP0INT
Endpoint 2 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 2
interrupt is enabled in UEPIEN.
Must be cleared by software.
2
1
0
Endpoint 1 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 1
interrupt is enabled in UEPIEN.
Must be cleared by software.
Endpoint 0 Interrupt Flag
Set by hardware when an interrupt is triggered in UEPSTAX and the endpoint 0
interrupt is enabled in UEPIEN.
Must be cleared by software.
Reset Value = 0000 0000b
Table 65. UEPIEN Register
UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3INTE
EP2INTE
EP1INTE
EP0INTE
78
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
