Bit
Bit
Number
Mnemonic Description
Function Enable Bit
Set to enable the function. The device firmware shall set this bit after it has
received a USB reset and participate in the following configuration process with
the default address (FEN is reset to 0).
7
FEN
Cleared by hardware at power-up, should not be cleared by the device firmware
once set.
USB Address Bits
This field contains the default address (0) after power-up or USB bus reset.
It shall be written with the value set by a SET_ADDRESS request received by
the device firmware.
6-0
UADD6:0
Reset Value = 0000 0000b
Table 58. USBINT Register
USBINT (S:BDh) – USB Global Interrupt Register
7
-
6
-
5
4
3
2
-
1
-
0
WUPCPU
EORINT
SOFINT
SPINT
Bit Bit
Number Mnemonic Description
Reserved
7 - 6
-
The values read from these Bits are always 0. Do not set these Bits.
Wake Up CPU Interrupt Flag
Set by hardware when the USB controller is in SUSPEND state and is re-activated
5
WUPCPU by a non-idle signal from USB line (not by an upstream resume). This triggers a USB
interrupt when EWUPCPU is set in the USBIEN.
Cleared by software after re-enabling all USB clocks.
End of Reset Interrupt Flag
Set by hardware when a End of Reset has been detected by the USB controller. This
4
EORINT
triggers a USB interrupt when EEORINT is set in USBIEN.
Cleared by software.
Start of Frame Interrupt Flag
Set by hardware when a USB Start of Frame packet (SOF) has been properly
SOFINT
3
2 - 1
0
received. This triggers a USB interrupt when ESOFINT is set in USBIEN.
Cleared by software.
Reserved
The values read from these Bits are always 0. Do not set these Bits.
-
Suspend Interrupt Flag
Set by hardware when a USB Suspend (Idle bus for three frame periods: a J state for
SPINT
3 ms) is detected. This triggers a USB interrupt when ESPINT is set in USBIEN.
Cleared by software.
Reset Value = 0000 0000b
Table 59. USBIEN Register
USBIEN (S:BEh) – USB Global Interrupt Enable Register
7
-
6
-
5
4
3
2
-
1
-
0
EWUPCPU EEORINT
ESOFINT
ESPINT
74
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
