AT89C5132
Bit
Number
Bit
Mnemonic Description
Control Endpoint Direction Bit
This bit is relevant only if the endpoint is configured in Control type.
Set for the data stage. Clear otherwise.
7
DIR
Note: This bit should be configured on RXSETUP interrupt before any other bit is
changed. This also determines the status phase (IN for a control write and OUT
for a control read). This bit should be cleared for status stage of a Control Out
transaction.
Reserved
6
5
-
The values read from this Bits are always 0. Do not set this bit.
Stall Handshake Request Bit
STALLRQ
Set to send a STALL answer to the host for the next handshake.Clear otherwise.
TX Packet Ready Control Bit
Set after a packet has been written into the endpoint FIFO for IN data transfers.
Data shall be written into the endpoint FIFO only after this bit has been cleared.
Set this bit without writing data to the endpoint FIFO to send a Zero Length
Packet, which is generally recommended and may be required to terminate a
transfer when the length of the last data packet is equal to MaxPacketSize (e.g.,
for control read transfers).
4
TXRDY
Cleared by hardware, as soon as the packet has been sent for Isochronous
endpoints, or after the host has acknowledged the packet for Control, Bulk and
Interrupt endpoints.
Stall Sent Interrupt Flag/CRC Error Interrupt Flag
For Control, Bulk and Interrupt Endpoints:
Set by hardware after a STALL handshake has been sent as requested by
STALLRQ. Then, the endpoint interrupt is triggered if enabled in UEPIEN.
3
STLCRC Cleared by hardware when a SETUP packet is received (see RXSETUP).
For Isochronous Endpoints:
Set by hardware if the last data received is corrupted (CRC error on data). Then,
the endpoint interrupt is triggered if enabled in UEPIEN.
Cleared by hardware when a non corrupted data is received.
Received SETUP Interrupt Flag
Set by hardware when a valid SETUP packet has been received from the host.
RXSETUP Then, all the other Bits of the register are cleared by hardware and the endpoint
interrupt is triggered if enabled in UEPIEN.
2
1
Clear by software after reading the SETUP data from the endpoint FIFO.
Received OUT Data Interrupt Flag
Set by hardware after an OUT packet has been received. Then, the endpoint
interrupt is triggered if enabled in UEPIEN and all the following OUT packets to
RXOUT
the endpoint are rejected (NACK’ed) until this bit is cleared. However, for Control
endpoints, an early SETUP transaction may overwrite the content of the endpoint
FIFO, even if its Data packet is received while this bit is set.
Clear by software after reading the OUT data from the endpoint FIFO.
Transmitted IN Data Complete Interrupt Flag
Set by hardware after an IN packet has been transmitted for Isochronous
endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk
and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in
UEPIEN.
0
TXCMP
Clear by software before setting again TXRDY.
Reset Value = 0000 0000b
Table 63. UEPRST Register
UEPRST (S:D5h) – USB Endpoint FIFO Reset Register
7
-
6
-
5
-
4
-
3
2
1
0
EP3RST
EP2RST
EP1RST
EP0RST
77
4173E–USB–09/07
ATMEL [ ATMEL ]
